1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device with a local sense amplifier that can be turned on only if required.
2. Description of the Related Art
In a semiconductor memory device such as a dynamic random access memory (DRAM) or a synchronous random access memory (SRAM), data read in a read operation sequentially passes through a plurality of sense amplifiers and is then output. Since data read from a memory cell has a low voltage, the voltage of the data is amplified by a bit line sense amplifier. The amplified voltage of the data is amplified again by a data sense amplifier, and then the data is output. FIG. 1 illustrates such a path of data read in a read operation.
FIG. 1 is a schematic circuit diagram of a conventional semiconductor memory device 100. The semiconductor memory device 100 includes a memory cell 110 in an array block, a word line WL and a pair of bit lines BL and /BL connected to the memory cell 110, an equalization circuit 120 that precharges the bit lines BL and /BL, a pair of local input/output (I/O) lines LIO and /LIO to be connected to the bit lines BL and /BL in response to a column selection line signal CSL, a pair of global I/O lines GIO and /GIO to be connected to the local I/O lines LIO and /LIO in response to a control signal LGIOMUX, a pair of data I/O lines DIO and /DIO to be connected to the global I/O lines GIO and /GIO in response to a control signal IOMUX, and a data sense amplifier 130.
As described above, a voltage of data stored in the memory cell 110 is amplified by a bit line sense amplifier (not shown) and the data sense amplifier 130, and then, the data is read at a high logic level or a low logic level.
More specifically, during a read operation of the semiconductor memory device 100, an /RAS active command (not shown) is activated to activate a word line connected to a memory cell of a row address from which the data is to be read. When the word line is activated, data stored in all memory cells connected to the activated word line is transmitted to bit lines corresponding to the memory cells, respectively.
Next, the bit line sense amplifier amplifies a voltage of data output from the bit lines BL and /BL according to a logic level of the data, i.e., at a high logic level or a low level. Next, the data output from the bit lines BL and /BL is transmitted to the data I/O lines DIO and /DIO in response to the column selection line signal CSL activated in response to a /CAS active command (not shown).
Recent trends have seen an increase in integration density of semiconductor memory devices and a reduction of a voltage thereof. An increase in the density results in an increase in the load capacitance across each pair of data lines, and a reduction in the voltage results in a reduction in the difference between voltages of the pairs of data lines applied to corresponding amplifiers.
Accordingly, it becomes more and more difficult for amplifiers to detect data with a minimum voltage difference and amplify voltages of the data. Further, semiconductor memory devices are required to operate at high speeds. tRCD, which is a major parameter for high-speed operation of semiconductor memory devices, denotes a duration between an execution of an /RAS active command and a /CAS active command, i.e., an /RAS to /CAS delay time. The lower the tRCD value, the faster an operating speed of a system using a DRAM.
FIG. 2A illustrates a tRCD parameter of a semiconductor memory device, which is the time interval between execution of an active command ACTIVE CMD and a read/write command READ/WRITE CMD. FIG. 2B illustrates a relationship between amplification of data output from a pair of bit lines and the tRCD parameter.
The tRCD parameter has a minimum value when the difference in voltage or current between data output from the data I/O lines DIO and /DIO has a minimum value that the data sense amplifier 130 can detect.
Referring to FIG. 2B, while the tRCD parameter can be reduced to a minimum value, in an internal operation of the semiconductor memory device 100 of FIG. 1, the lower the tRCD value, the more likely it is that the column selection line signal CSL will be activated before voltages of data output from the bit lines BL and /BL are completely amplified. Thus, the difference in voltage or current between data output from the data I/O lines DIO and /DIO to be applied to the data sense amplifier 130 becomes reduced. If the difference in voltage or current is too small for the data sense amplifier 130 to detect, incorrect data may be read.